000			06176nam a2201165 i 4500
001			5237648
003			IEEE
005			20230927112344.0
006			m o d
007			cr |n|||||||||
008			151221s2006 njua ob 001 eng d
020			_a9780471786412 _qebook
020			_a9786610448104
020			_z6610448108
020			_z9780471720928 _qprint
020			_z0471720925 _qalk. paper
020			_z0471786411 _qelectronic
020			_z047178639X _qelectronic
020			_z9780471786399 _qelectronic
024	7		_a10.1002/0471786411 _2doi
035			_a(CaBNVSL)mat05237648
035			_a(IDAMS)0b00006481095a71
040			_aCaBNVSL _beng _erda _cCaBNVSL _dCaBNVSL
082	0	4	_a621.39/2
100	1		_aChu, Pong P., _d1959-
245	1	0	_aRTL hardware design using VHDL : _bcoding for efficiency, portability, and scalability / _cPong P. Chu.
264		1	_aHoboken, New Jersey : _bWiley-Interscience, _cc2006.
264		2	_a[Piscataqay, New Jersey] : _bIEEE Xplore, _c[2006]
300			_a1 PDF (xxiii, 669 pages) : _billustrations.
336			_atext _2rdacontent
337			_aelectronic _2isbdmedia
338			_aonline resource _2rdacarrier
504			_aIncludes bibliographical references (p. 665-666) and index.
505	0		_aIntroduction to digital system design -- Overview of hardware description languages -- Basic language constructs of VHDL -- Concurrent signal assignment statements of VHDL -- Sequential statements of VHDL -- Synthesis of VHDL code -- Combinational circuit design : practice -- Sequential circuit design : principle -- Sequential circuit design : practice -- Finite state machine : principle and practice -- Register transfer methodology : principle -- Register transfer methodology : practice -- Hierarchical design in VHDL -- Parameterized design : principle -- Parameterized design : practice -- Clock and synchronization : principle and practice.
506	1		_aRestricted to subscribers or individual electronic text purchasers.
520			_aThe skills and guidance needed to master RTL hardware design This book teaches readers how to systematically design efficient, portable, and scalable Register Transfer Level (RTL) digital circuits using the VHDL hardware description language and synthesis software. Focusing on the module-level design, which is composed of functional units, routing circuit, and storage, the book illustrates the relationship between the VHDL constructs and the underlying hardware components, and shows how to develop codes that faithfully reflect the module-level design and can be synthesized into efficient gate-level implementation. Several unique features distinguish the book: * Coding style that shows a clear relationship between VHDL constructs and hardware components * Conceptual diagrams that illustrate the realization of VHDL codes * Emphasis on the code reuse * Practical examples that demonstrate and reinforce design concepts, procedures, and techniques * Two chapters on realizing sequential algorithms in hardware * Two chapters on scalable and parameterized designs and coding * One chapter covering the synchronization and interface between multiple clock domains Although the focus of the book is RTL synthesis, it also examines the synthesis task from the perspective of the overall development process. Readers learn good design practices and guidelines to ensure that an RTL design can accommodate future simulation, verification, and testing needs, and can be easily incorporated into a larger system or reused. Discussion is independent of technology and can be applied to both ASIC and FPGA devices. With a balanced presentation of fundamentals and practical examples, this is an excellent textbook for upper-level undergraduate or graduate courses in advanced digital logic. Engineers who need to make effective use of today's synthesis software and FPGA devices should also refer to this book.
530			_aAlso available in print.
538			_aMode of access: World Wide Web
550			_aMade available online by EBSCO.
588			_aDescription based on PDF viewed 12/21/2015.
650		0	_aDigital electronics _xData processing.
650		0	_aVHDL (Computer hardware description language)
655		0	_aElectronic books.
695			_aAdders
695			_aAggregates
695			_aAlgorithm design and analysis
695			_aApplication specific integrated circuits
695			_aArrays
695			_aBibliographies
695			_aBooks
695			_aClocks
695			_aComplexity theory
695			_aComputational modeling
695			_aComputer architecture
695			_aDecoding
695			_aDelay
695			_aDesign methodology
695			_aDigital systems
695			_aEncoding
695			_aField programmable gate arrays
695			_aFinite element methods
695			_aGenerators
695			_aHardware
695			_aHardware design languages
695			_aHeuristic algorithms
695			_aIEEE standards
695			_aIndexes
695			_aIntegrated circuit interconnections
695			_aIntegrated circuit modeling
695			_aLatches
695			_aLibraries
695			_aLogic gates
695			_aMemory management
695			_aMultiplexing
695			_aOrganizations
695			_aProcess control
695			_aPulse generation
695			_aRadiation detectors
695			_aRandom access memory
695			_aReceivers
695			_aRegisters
695			_aRouting
695			_aSections
695			_aSemantics
695			_aSensitivity
695			_aSequential circuits
695			_aSkeleton
695			_aSoftware
695			_aSoftware algorithms
695			_aSynchronization
695			_aSyntactics
695			_aTime factors
695			_aTiming
695			_aTransistors
710	2		_aJohn Wiley & Sons, _epublisher.
710	2		_aIEEE Xplore (Online service), _edistributor.
776	0	8	_iPrint version: _z9780471720928
856	4	2	_3Abstract with links to resource _uhttps://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5237648
999			_c40049 _d40049