Advances in embedded and fan-out wafer level packaging technologies / (Record no. 40869)

MARC details
000 -LEADER
fixed length control field 07144nam a2200577 i 4500
001 - CONTROL NUMBER
control field 8726249
003 - CONTROL NUMBER IDENTIFIER
control field IEEE
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20230927112401.0
006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS
fixed length control field m o d
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
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008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 190614s2019 mau ob 001 eng d
010 ## - LIBRARY OF CONGRESS CONTROL NUMBER
Canceled/invalid LC control number 2018037473 (print)
019 ## -
-- 1089126008
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781119313991
Qualifying information electronic book
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
Canceled/invalid ISBN 9781119313977
Qualifying information electronic book
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
Canceled/invalid ISBN 111931397X
Qualifying information electronic book
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
Canceled/invalid ISBN 9781119314134
Qualifying information print
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
Canceled/invalid ISBN 9781119313984
Qualifying information electronic book
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
Canceled/invalid ISBN 1119313988
Qualifying information electronic book
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
Canceled/invalid ISBN 1119313996
Qualifying information electronic book
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.1002/9781119313991
Source of number or code doi
035 ## - SYSTEM CONTROL NUMBER
System control number (CaBNVSL)mat08726249
035 ## - SYSTEM CONTROL NUMBER
System control number (IDAMS)0b0000648935c166
040 ## - CATALOGING SOURCE
Original cataloging agency CaBNVSL
Language of cataloging eng
Description conventions rda
Transcribing agency CaBNVSL
Modifying agency CaBNVSL
082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.39/5
245 00 - TITLE STATEMENT
Title Advances in embedded and fan-out wafer level packaging technologies /
Statement of responsibility, etc. edited by Beth Keser and Steffen Kr�ohnert.
264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE
Place of production, publication, distribution, manufacture Hoboken, New Jersey, USA :
Name of producer, publisher, distributor, manufacturer John Wiley & Sons, Inc.,
Date of production, publication, distribution, manufacture, or copyright notice 2019.
264 #2 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE
Place of production, publication, distribution, manufacture [Piscataqay, New Jersey] :
Name of producer, publisher, distributor, manufacturer IEEE Xplore,
Date of production, publication, distribution, manufacture, or copyright notice [2019]
300 ## - PHYSICAL DESCRIPTION
Extent 1 PDF (576 pages).
336 ## - CONTENT TYPE
Content type term text
Source rdacontent
337 ## - MEDIA TYPE
Media type term electronic
Source isbdmedia
338 ## - CARRIER TYPE
Carrier type term online resource
Source rdacarrier
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc. note Includes bibliographical references and index.
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Preface xvii -- List of Contributors xxiii -- Acknowledgments xxvii -- 1 History of Embedded and Fan-Out Packaging Technology 1 /Michael Topper, Andreas Ostmann, Tanja Braun, and Klaus-Dieter Lang -- 2 FO-WLP Market and Technology Trends 39 /E. Jan Vardaman -- 3 Embedded Wafer-Level Ball Grid Array (eWLB) Packaging Technology Platform 55 /Thorsten Meyer and Steffen Krohnert -- 4 Ultrathin 3D FO-WLP eWLB-PoP (Embedded Wafer-Level Ball Grid Array-Package-on-Package) Technology 77 /S.W. Yoon -- 5 NEPES’ Fan-Out Packaging Technology from Single die, SiP to Panel-Level Packaging 97 /Jong Heon (Jay) Kim -- 6 M-Series Fan-Out with Adaptive Patterning 117 /Tim Olson and Chris Scanlan -- 7 SWIFTR Semiconductor Packaging Technology 141 /Ron Huemoeller and Curtis Zwenger -- 8 Embedded Silicon Fan-Out (eSiFOR) Technology for Wafer-Level System Integration 169 /Daquan Yu -- 9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i2 Board Technology 185 /Thomas Gottwald, Christian Roessle, and Alexander Neumann -- 10 Embedding of Power Electronic Components: The Smart p2 Pack Technology 201 /Thomas Gottwald and Christian Roessle -- 11 Embedded Die in Substrate (Panel-Level) Packaging Technology 217 /Tomoko Takahashi and Akio Katsumata -- 12 Blade: A Chip-First Embedded Technology for Power Packaging 241 /Boris Plikat and Thorsten Scharf -- 13 The Role of Liquid Molding Compounds in the Success of Fan-Out Wafer-Level Packaging Technology 261 /Katsushi Kan, Michiyasu Sugahara, and Markus Cichon -- 14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan-Out Wafer-Level Packaging (FO-WLP) 271 /T. Enomoto, J.I. Matthews, and T. Motobe -- 15 Enabling Low Temperature Cure Dielectrics for Advanced Wafer-Level Packaging 317 /Stefan Vanclooster and Dimitri Janssen -- 16 The Role of Pick and Place in Fan-Out Wafer-Level Packaging 347 /Hugo Pristauz, Alastair Attard, and Harald Meixner -- 17 Process and Equipment for eWLB: Chip Embedding by Molding 371 /Edward Furgut, Hirohito Oshimori, and Hiroaki Yamagishi.
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 18 Tools for Fan-Out Wafer-Level Package Processing 403 /Nelson Fan, Eric Kuah, Eric Ng, and Otto Cheung -- 19 Equipment and Process for eWLB: Required PVD/Sputter Solutions 419 /Chris Jones, Ricardo Gaio, and Jose Castro -- 20 Excimer Laser Ablation for the Patterning of Ultra-fine Routings 441 /Habib Hichri, Markus Arendt, and Seongkuk Lee -- 21 Temporary Carrier Technologies for eWLB and RDL-First Fan-Out Wafer-Level Packages 457 /Thomas Uhrmann and Boris Povazay -- 22 Encapsulated Wafer-Level Package Technology (eWLCSP): Robust WLCSP Reliability with Sidewall Protection 471 /S.W. Yoon -- 23 Embedded Multi-die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect 487 /Ravi Mahajan, Robert Sankman, Kemal Aygun, Zhiguo Qian, Ashish Dhall, Jonathan Rosch, Debendra Mallik, and Islam Salama -- 24 Interconnection Technology Innovations in 2.5D Integrated Electronic Systems 501 /Paragkumar A. Thadesar, Paul K. Jo, and Muhannad S. Bakir -- References 515 -- Index 521.
506 ## - RESTRICTIONS ON ACCESS NOTE
Terms governing access Restricted to subscribers or individual electronic text purchasers.
520 ## - SUMMARY, ETC.
Summary, etc. Examines the advantages of Embedded and FO-WLP technologies, potential application spaces, package structures available in the industry, process flows, and material challenges Embedded and fan-out wafer level packaging "FO-WLP" technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for nearly a decade. This book covers the advances that have been made in this new packaging technology and discusses the many benefits it provides to the electronic packaging industry and supply chain. It provides a compact overview of the major types of technologies offered in this field, on what is available, how it is processed, what is driving its development, and the pros and cons. Filled with contributions from some of the field's leading experts,??Advances in Embedded and Fan-Out Wafer Level Packaging Technologies??begins with a look at the history of the technology. It then goes on to examine the biggest technology and marketing trends. Other sections are dedicated to chip-first FO-WLP, chip-last FO-WLP, embedded die packaging, materials challenges, equipment challenges, and resulting technology fusions. This valuable text: . Discusses specific company standards and their development results. Relates its content to practice as well as to contemporary and future challenges in electronics system integration and packaging Advances in Embedded and Fan-Out Wafer Level Packaging Technologies??will appeal to microelectronic packaging engineers, managers, and decision makers working in OEMs, IDMs, IFMs, OSATs, silicon foundries, materials suppliers, equipment suppliers, and CAD tool suppliers. It is also an excellent book for professors and graduate students working in microelectronic packaging research.
530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE
Additional physical form available note Also available in print.
538 ## - SYSTEM DETAILS NOTE
System details note Mode of access: World Wide Web
588 ## - SOURCE OF DESCRIPTION NOTE
Source of description note Description based on online resource; title from digital title page (viewed on May 17, 2019).
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Chip scale packaging.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Integrated circuits
General subdivision Wafer-scale integration.
655 #0 - INDEX TERM--GENRE/FORM
Genre/form data or focus term Electronic books.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Keser, Beth,
Dates associated with a name 1971-
Relator term editor.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Kroehnert, Steffen,
Dates associated with a name 1970-
Relator term editor.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element IEEE Xplore (Online Service),
Relator term distributor.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element Wiley,
Relator term publisher.
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Relationship information Print version:
Title Advances in embedded and fan-out wafer level packaging technologies.
Edition 1st edition.
Place, publisher, and date of publication Hoboken, NJ, USA : Wiley, [2018]
International Standard Book Number 9781119314134
Record control number (DLC) 2018034374
856 42 - ELECTRONIC LOCATION AND ACCESS
Materials specified Abstract with links to resource
Uniform Resource Identifier <a href="https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=8726249">https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=8726249</a>

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