Design for embedded image processing on FPGAs / (Record no. 40452)
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| fixed length control field | 08408nam a2201201 i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 6016259 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | IEEE |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20230927112353.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS | |
| fixed length control field | m o d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr |n||||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 151221s2011 njua ob 001 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9780470828519 |
| Qualifying information | ebook |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 9780470828496 |
| Qualifying information | |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 047082851X |
| Qualifying information | electronic |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1002/9780470828519 |
| Source of number or code | doi |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (CaBNVSL)mat06016259 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (IDAMS)0b0000648164c992 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | CaBNVSL |
| Language of cataloging | eng |
| Description conventions | rda |
| Transcribing agency | CaBNVSL |
| Modifying agency | CaBNVSL |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.39/9 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Bailey, Donald G. |
| Fuller form of name | (Donald Graeme), |
| Dates associated with a name | 1962- |
| 245 10 - TITLE STATEMENT | |
| Title | Design for embedded image processing on FPGAs / |
| Statement of responsibility, etc. | Donald G. Bailey. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | New York, NY : |
| Name of producer, publisher, distributor, manufacturer | Wiley, |
| Date of production, publication, distribution, manufacture, or copyright notice | 2011. |
| 264 #2 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | [Piscataqay, New Jersey] : |
| Name of producer, publisher, distributor, manufacturer | IEEE Xplore, |
| Date of production, publication, distribution, manufacture, or copyright notice | [2011] |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1 PDF (xvi, 482 pages) : |
| Other physical details | illustrations (some color). |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | electronic |
| Source | isbdmedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Source | rdacarrier |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE | |
| Bibliography, etc. note | Includes bibliographical references. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Preface -- Acknowledgements -- 1 Image Processing -- 1.1 Basic Definitions -- 1.2 Image Formation -- 1.3 Image Processing Operations -- 1.4 Example Application -- 1.5 Real-Time Image Processing -- 1.6 Embedded Image Processing -- 1.7 Serial Processing -- 1.8 Parallelism -- 1.9 Hardware Image Processing Systems -- 2 Field Programmable Gate Arrays -- 2.1 Programmable Logic -- 2.2 FPGAs and Image Processing -- 2.3 Inside an FPGA -- 2.4 FPGA Families and Features -- 2.5 Choosing an FPGA or Development Board -- 3 Languages -- 3.1 Hardware Description Languages -- 3.2 Software-Based Languages -- 3.3 Visual Languages -- 3.4 Summary -- 4 Design Process -- 4.1 Problem Specification -- 4.2 Algorithm Development -- 4.3 Architecture Selection -- 4.4 System Implementation -- 4.5 Designing for Tuning and Debugging -- 5 Mapping Techniques -- 5.1 Timing Constraints -- 5.2 Memory Bandwidth Constraints -- 5.3 Resource Constraints -- 5.4 Computational Techniques -- 5.5 Summary -- 6 Point Operations -- 6.1 Point Operations on a Single Image -- 6.2 Point Operations on Multiple Images -- 6.3 Colour Image Processing -- 6.4 Summary -- 7 Histogram Operations -- 7.1 Greyscale Histogram -- 7.2 Multidimensional Histograms -- 8 Local Filters -- 8.1 Caching -- 8.2 Linear Filters -- 8.3 Nonlinear Filters -- 8.4 Rank Filters -- 8.5 Colour Filters -- 8.6 Morphological Filters -- 8.7 Adaptive Thresholding -- 8.8 Summary -- 9 Geometric Transformations -- 9.1 Forward Mapping -- 9.2 Reverse Mapping -- 9.3 Interpolation -- 9.4 Mapping Optimisations -- 9.5 Image Registration -- 10 Linear Transforms -- 10.1 Fourier Transform -- 10.2 Discrete Cosine Transform -- 10.3 Wavelet Transform -- 10.4 Image and Video Coding -- 11 Blob Detection and Labelling -- 11.1 Bounding Box -- 11.2 Run-Length Coding -- 11.3 Chain Coding -- 11.4 Connected Component Labelling -- 11.5 Distance Transform -- 11.6 Watershed Transform -- 11.7 Hough Transform -- 11.8 Summary -- 12 Interfacing -- 12.1 Camera Input -- 12.2 Display Output. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 12.3 Serial Communication -- 12.4 Memory -- 12.5 Summary -- 13 Testing, Tuning and Debugging -- 13.1 Design -- 13.2 Implementation -- 13.3 Tuning -- 13.4 Timing Closure -- 14 Example Applications -- 14.1 Coloured Region Tracking -- 14.2 Lens Distortion Correction -- 14.3 Foveal Sensor -- 14.4 Range Imaging -- 14.5 Real-Time Produce Grading -- 14.6 Summary -- References -- Index. |
| 506 1# - RESTRICTIONS ON ACCESS NOTE | |
| Terms governing access | Restricted to subscribers or individual electronic text purchasers. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | Dr Donald Bailey starts with introductory material considering the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine-grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The design process for implementing an image processing algorithm on an FPGA is compared with that for a conventional software implementation, with the key differences highlighted. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage is given of a range of low and intermediate level image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques are illustrated with several example applications or case studies from projects or applications the author has been involved with. Issues such as interfacing between the FPGA and peripheral devices are covered briefly, as is designing the system in such a way that it can be more readily debugged and tuned.. Provides a bridge between algorithms and hardware. Demonstrates how to avoid many of the potential pitfalls. Offers practical recommendations and solutions. Illustrates several real-world applications and case studies. Allows those with software backgrounds to understand efficient hardware implementationDesign for Embedded Image Processing on FPGAs is ideal for researchers and engineers in the vision or image processing industry, who are looking at smart sensors, machine vision, and robotic vision, as well as FPGA developers and application engineers.The book can also be used by graduate students studying imaging systems, computer engineering, digital design, circuit design, or computer science. It can also be used as supplementary text for courses in advanced digital design, algorithm and hardware implementation, and digital signal processing and applications.Lecture slides for instructors available at:www.wiley.com/go/bailey/fpga. |
| 530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE | |
| Additional physical form available note | Also available in print. |
| 538 ## - SYSTEM DETAILS NOTE | |
| System details note | Mode of access: World Wide Web |
| 588 ## - SOURCE OF DESCRIPTION NOTE | |
| Source of description note | Description based on PDF viewed 12/21/2015. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Embedded computer systems. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Field programmable gate arrays. |
| 655 #0 - INDEX TERM--GENRE/FORM | |
| Genre/form data or focus term | Electronic books. |
| 695 ## - | |
| -- | Algorithm design and analysis |
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| -- | Bandwidth |
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| -- | Bibliographies |
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| -- | Cameras |
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| -- | Clocks |
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| -- | Codecs |
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| -- | Color |
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| -- | Computer architecture |
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| -- | Computers |
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| -- | Digital images |
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| -- | Equations |
| 695 ## - | |
| -- | Fast Fourier transforms |
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| -- | Field programmable gate arrays |
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| -- | Frequency domain analysis |
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| -- | Generators |
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| -- | Hardware |
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| -- | Heuristic algorithms |
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| -- | Histograms |
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| -- | IEEE 1394 Standard |
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| -- | Image coding |
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| -- | Image color analysis |
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| -- | Image edge detection |
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| -- | Image processing |
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| -- | Image segmentation |
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| -- | Image sensors |
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| -- | Indexes |
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| -- | Integrated circuit interconnections |
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| -- | Integrated circuit modeling |
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| -- | Iron |
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| -- | Labeling |
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| -- | Lenses |
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| -- | Lighting |
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| -- | Logic gates |
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| -- | Mathematical model |
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| -- | Memory management |
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| -- | Multiplexing |
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| -- | Nanometers |
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| -- | Noise |
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| -- | PROM |
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| -- | Pipeline processing |
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| -- | Pipelines |
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| -- | Propagation delay |
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| -- | Protocols |
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| -- | Radiation detectors |
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| -- | Random access memory |
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| -- | Registers |
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| -- | Sensors |
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| -- | Shift registers |
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| -- | Software algorithms |
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| -- | Streaming media |
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| -- | Switches |
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| -- | Synchronization |
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| -- | Table lookup |
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| -- | Testing |
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| -- | Transfer functions |
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| -- | Transforms |
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| -- | Universal Serial Bus |
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| -- | Wheels |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | IEEE Xplore (Online Service), |
| Relator term | distributor. |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | John Wiley & Sons, |
| Relator term | publisher. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Print version: |
| International Standard Book Number | 9780470828496 |
| 856 42 - ELECTRONIC LOCATION AND ACCESS | |
| Materials specified | Abstract with links to resource |
| Uniform Resource Identifier | <a href="https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6016259">https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6016259</a> |
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