Computer-aided design of analog integrated circuits and systems / (Record no. 40204)
[ view plain ]
| 000 -LEADER | |
|---|---|
| fixed length control field | 12733nam a2202317 i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 5265766 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | IEEE |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20230927112347.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS | |
| fixed length control field | m o d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr |n||||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 100317t20152002njua ob 000 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9780470544310 |
| Qualifying information | electronic |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 9780471227823 |
| Qualifying information | |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 0470544317 |
| Qualifying information | electronic |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1109/9780470544310 |
| Source of number or code | doi |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (CaBNVSL)mat05265766 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (IDAMS)0b000064810c58ea |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | CaBNVSL |
| Language of cataloging | eng |
| Description conventions | rda |
| Transcribing agency | CaBNVSL |
| Modifying agency | CaBNVSL |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.38150285 |
| 245 00 - TITLE STATEMENT | |
| Title | Computer-aided design of analog integrated circuits and systems / |
| Statement of responsibility, etc. | edited by Rob A. Rutenbar, Georges G.E. Gielen, Brian A. Antao. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | Piscataway, New Jersey : |
| Name of producer, publisher, distributor, manufacturer | IEEE Press, |
| Date of production, publication, distribution, manufacture, or copyright notice | c2002. |
| 264 #2 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | [Piscataqay, New Jersey] : |
| Name of producer, publisher, distributor, manufacturer | IEEE Xplore, |
| Date of production, publication, distribution, manufacture, or copyright notice | [2002] |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1 PDF (xi, 754 pages) : |
| Other physical details | illustrations. |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | electronic |
| Source | isbdmedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Source | rdacarrier |
| 500 ## - GENERAL NOTE | |
| General note | "A selected reprint volume." |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE | |
| Bibliography, etc. note | Includes bibliographical references. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Preface -- Acknowledgments -- Computer-Aided Design of Analog and Mixed-Signal Integrated Circuits -- Design of Mixed-Signal Systems-on-a-Chip -- IDAC: An Interactive Design Tool for Analog CMOS Circuits -- OPASYN: A Compliler for CMOS Operational Amplifiers -- OASYS: A Framework for Analog Circuit Synthesis -- Analog Circuit Design Optimization Based on Symbolic Simulation and Simulated Annealing -- STAIC: An Interactive Framework for Synthesizing CMOS and BiCMOS Analog Circuits -- Integer Programming Based Topology Selection of Cell-Level Analog Circuits -- ARCHGEN: Automated Synthesis of Analog Systems -- DARWIN: CMOS Opamp Synthesis by Means of a Genetic Algorithm -- AMGIE: A Synthesis Environment for CMOS Analog Integrated Circuits -- A High-Level Design and Optimization Tool for Analog RF Receiver Front-Ends -- A Statistical Optimization-Based Approach for Automated Sizing of Analog Cells -- Synthesis of High-Performance Analog Circuits in ASTRX/OBLX -- MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells -- Anaconda: Simulation-Based Synthesis of Analog Circuits Via Stochastic Pattern Search -- A Case Study of Synthesis for Industrial-Scale Analog IP: Redesign of the Equalizer/Filter Frontend for an ADSL CODEC -- WiCkeD: Analog Circuit Synthesis Incorporating Mismatch -- Optimal Design of a CMOS Op-Amp via Geometric Programming -- Techniques and Applications of Symbolic Analysis for Analog Integrated Circuits: A Tutorial Overview -- Flowgraph Analysis of Large Electronic Networks -- ISAAC: A Symbolic Simulator for Analog Integrated Circuits -- Interactive AC Modeling and Characterization of Analog Circuits via Symbolic Analysis -- SSCNAP: A Program for Symbolic Analysis of Switched Capacitor Circuits -- Efficient Symbolic Computation of Approximated Small-Signal Characteristics of Analog Integrated Circuits -- Efficient Approximation of Symbolic Network Functions Using Matroid Intersection Algorithms -- High-Frequency Distortion Analysis of Analog Integrated Circuits. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Canonical Symbolic Analysis of Large Analog Circuits with Determinant Decision Diagrams -- Layout Tools for Analog ICs and Mixed-Signal SoCs: A Survey -- ILAC: An Automated Layout Tool for Analog CMOS Circuits -- KOAN/ANAGRAM II: New Tools for Device-Level Analog Placement and Routing -- Automatic Generation of Parasitic Constraints for Performance-Constrained Physical Design of Analog Circuits -- Performance-Driven Compaction for Analog Integrated Circuits -- Automation of IC Layout with Analog Constraints -- A Performance-Driven Placement Tool for Analog Integrated Circuits -- Optimum CMOS Stack Generation with Analog Constraints -- Substrate-Aware Mixed-Signal Macrocell Placement in WRIGHT -- System-Level Routing of Mixed-Signal ASICs in WREN -- Addressing Substrate Coupling in Mixed-Mode IC's: Simulation and Power Distribution Synthesis -- Mondriaan: A Tool for Automated Layout Synthesis of Array-Type Analog Blocks -- Device-Level Early Floorplanning Algorithms for RF Circuits -- Macromodeling of Integrated Circuit Operational Amplifiers -- A Macromodeling Algorithm for Analog Circuits -- Consistency Checking and Optimization of Macromodels -- Computer-Aided Design Considerations for Mixed-Signal Coupling in RF Integrated Circuits -- Integration and Electrical Isolation in CMOS Mixed-Signal Wireless Chips -- Simulating and Testing Oversampled Analog-to-Digital Converters -- Simulation of Mixed Switched-Capacitor/Digital Networks with Signal-Driven Switches -- Behavioral Simulation for Analog System Design Verification -- Multilevel and Mixed-Domain Simulation of Analog Circuits and Systems -- Simulation Methods for RF Integrated Circuits -- VHDL-AMS - A Hardware Description Language for Analog and Mixed-Signal Applications -- DELIGHT.SPICE: An Optimization-Based System for the Design of Integrated Circuits -- Design Centering by Yield Prediction -- Statistical Integrated Circuit Design -- Yield Optimization of Analog IC's Using Two-Step Analytic Modeling Methods. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Circuit Analysis and Optimization Driven by Worst-Case Distances -- Efficient Analog Circuit Synthesis with Simultaneous Yield and Robustness Optimization -- Efficient Handling of Operating Range and Manufacturing Line Variations in Analog Cell Synthesis -- The Generalized Boundary Curve - A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits -- Metrics, Techniques and Recent Developments in Mixed-Signal Testing -- A Tutorial Introduction to Research on Analog and Mixed-Signal Circuit Testing -- About the Editors. |
| 506 1# - RESTRICTIONS ON ACCESS NOTE | |
| Terms governing access | Restricted to subscribers or individual electronic text purchasers. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | The tools and techniques you need to break the analog design bottleneck! Ten years ago, analog seemed to be a dead-end technology. Today, System-on-Chip (SoC) designs are increasingly mixed-signal designs. With the advent of application-specific integrated circuits (ASIC) technologies that can integrate both analog and digital functions on a single chip, analog has become more crucial than ever to the design process. Today, designers are moving beyond hand-crafted, one-transistor-at-a-time methods. They are using new circuit and physical synthesis tools to design practical analog circuits; new modeling and analysis tools to allow rapid exploration of system level alternatives; and new simulation tools to provide accurate answers for analog circuit behaviors and interactions that were considered impossible to handle only a few years ago. To give circuit designers and CAD professionals a better understanding of the history and the current state of the art in the field, this volume collects in one place the essential set of analog CAD papers that form the foundation of today's new analog design automation tools. Areas covered are: . Analog synthesis. Symbolic analysis. Analog layout. Analog modeling and analysis. Specialized analog simulation. Circuit centering and yield optimization. Circuit testing Computer-Aided Design of Analog Integrated Circuits and Systems is the cutting-edge reference that will be an invaluable resource for every semiconductor circuit designer and CAD professional who hopes to break the analog design bottleneck. |
| 530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE | |
| Additional physical form available note | Also available in print. |
| 538 ## - SYSTEM DETAILS NOTE | |
| System details note | Mode of access: World Wide Web |
| 588 ## - SOURCE OF DESCRIPTION NOTE | |
| Source of description note | Description based on PDF viewed 12/21/2015. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Integrated circuits |
| General subdivision | Computer-aided design. |
| 655 #0 - INDEX TERM--GENRE/FORM | |
| Genre/form data or focus term | Electronic books. |
| 695 ## - | |
| -- | Noise |
| 695 ## - | |
| -- | Numerical models |
| 695 ## - | |
| -- | Numerical simulation |
| 695 ## - | |
| -- | Object oriented modeling |
| 695 ## - | |
| -- | Operational amplifiers |
| 695 ## - | |
| -- | Optimization |
| 695 ## - | |
| -- | Optimization methods |
| 695 ## - | |
| -- | Organizations |
| 695 ## - | |
| -- | Partitioning algorithms |
| 695 ## - | |
| -- | Peer to peer computing |
| 695 ## - | |
| -- | Performance evaluation |
| 695 ## - | |
| -- | Pins |
| 695 ## - | |
| -- | Pluto |
| 695 ## - | |
| -- | Poles and zeros |
| 695 ## - | |
| -- | Polynomials |
| 695 ## - | |
| -- | Positron emission tomography |
| 695 ## - | |
| -- | Production |
| 695 ## - | |
| -- | Programming |
| 695 ## - | |
| -- | RLC circuits |
| 695 ## - | |
| -- | Radio frequency |
| 695 ## - | |
| -- | Receivers |
| 695 ## - | |
| -- | Resistors |
| 695 ## - | |
| -- | Resource management |
| 695 ## - | |
| -- | Robustness |
| 695 ## - | |
| -- | Routing |
| 695 ## - | |
| -- | SPICE |
| 695 ## - | |
| -- | Schedules |
| 695 ## - | |
| -- | Semantics |
| 695 ## - | |
| -- | Semiconductor process modeling |
| 695 ## - | |
| -- | Sensitivity |
| 695 ## - | |
| -- | Shape |
| 695 ## - | |
| -- | Signal to noise ratio |
| 695 ## - | |
| -- | Solid modeling |
| 695 ## - | |
| -- | Space exploration |
| 695 ## - | |
| -- | Sparse matrices |
| 695 ## - | |
| -- | Stochastic processes |
| 695 ## - | |
| -- | Substrates |
| 695 ## - | |
| -- | Switches |
| 695 ## - | |
| -- | Switching circuits |
| 695 ## - | |
| -- | System-on-a-chip |
| 695 ## - | |
| -- | Testing |
| 695 ## - | |
| -- | Time domain analysis |
| 695 ## - | |
| -- | Time frequency analysis |
| 695 ## - | |
| -- | Timing |
| 695 ## - | |
| -- | Topology |
| 695 ## - | |
| -- | Trademarks |
| 695 ## - | |
| -- | Transceivers |
| 695 ## - | |
| -- | Transconductance |
| 695 ## - | |
| -- | Transfer functions |
| 695 ## - | |
| -- | Transient analysis |
| 695 ## - | |
| -- | Transistors |
| 695 ## - | |
| -- | Turbo codes |
| 695 ## - | |
| -- | Uncertainty |
| 695 ## - | |
| -- | Vectors |
| 695 ## - | |
| -- | Viterbi algorithm |
| 695 ## - | |
| -- | Wire |
| 695 ## - | |
| -- | Wireless communication |
| 695 ## - | |
| -- | Wires |
| 695 ## - | |
| -- | Wiring |
| 695 ## - | |
| -- | Yield estimation |
| 695 ## - | |
| -- | Accuracy |
| 695 ## - | |
| -- | Admittance |
| 695 ## - | |
| -- | Algorithm design and analysis |
| 695 ## - | |
| -- | Analog circuits |
| 695 ## - | |
| -- | Analog integrated circuits |
| 695 ## - | |
| -- | Analog-digital conversion |
| 695 ## - | |
| -- | Analytical models |
| 695 ## - | |
| -- | Annealing |
| 695 ## - | |
| -- | Anodes |
| 695 ## - | |
| -- | Application specific integrated circuits |
| 695 ## - | |
| -- | Approximation algorithms |
| 695 ## - | |
| -- | Approximation methods |
| 695 ## - | |
| -- | Arrays |
| 695 ## - | |
| -- | Artificial intelligence |
| 695 ## - | |
| -- | Assembly |
| 695 ## - | |
| -- | Atmospheric modeling |
| 695 ## - | |
| -- | Biographies |
| 695 ## - | |
| -- | Bismuth |
| 695 ## - | |
| -- | Built-in self-test |
| 695 ## - | |
| -- | CMOS integrated circuits |
| 695 ## - | |
| -- | Capacitance |
| 695 ## - | |
| -- | Capacitors |
| 695 ## - | |
| -- | Cathodes |
| 695 ## - | |
| -- | Central Processing Unit |
| 695 ## - | |
| -- | Circuit analysis |
| 695 ## - | |
| -- | Circuit faults |
| 695 ## - | |
| -- | Circuit simulation |
| 695 ## - | |
| -- | Circuit synthesis |
| 695 ## - | |
| -- | Clocks |
| 695 ## - | |
| -- | Compaction |
| 695 ## - | |
| -- | Computational modeling |
| 695 ## - | |
| -- | Computer architecture |
| 695 ## - | |
| -- | Computers |
| 695 ## - | |
| -- | Converters |
| 695 ## - | |
| -- | Convex functions |
| 695 ## - | |
| -- | Convolution |
| 695 ## - | |
| -- | Cooling |
| 695 ## - | |
| -- | Cost function |
| 695 ## - | |
| -- | Couplings |
| 695 ## - | |
| -- | Databases |
| 695 ## - | |
| -- | Decoding |
| 695 ## - | |
| -- | Degradation |
| 695 ## - | |
| -- | Delta modulation |
| 695 ## - | |
| -- | Design automation |
| 695 ## - | |
| -- | Digital circuits |
| 695 ## - | |
| -- | Distortion |
| 695 ## - | |
| -- | Distortion measurement |
| 695 ## - | |
| -- | Eigenvalues and eigenfunctions |
| 695 ## - | |
| -- | Engines |
| 695 ## - | |
| -- | Equalizers |
| 695 ## - | |
| -- | Equations |
| 695 ## - | |
| -- | Finite element methods |
| 695 ## - | |
| -- | Finite impulse response filter |
| 695 ## - | |
| -- | Fluctuations |
| 695 ## - | |
| -- | Frequency conversion |
| 695 ## - | |
| -- | Frequency domain analysis |
| 695 ## - | |
| -- | Frequency estimation |
| 695 ## - | |
| -- | Frequency modulation |
| 695 ## - | |
| -- | Gain |
| 695 ## - | |
| -- | Generators |
| 695 ## - | |
| -- | Geometry |
| 695 ## - | |
| -- | Graphics |
| 695 ## - | |
| -- | Hardware |
| 695 ## - | |
| -- | Hardware design languages |
| 695 ## - | |
| -- | Harmonic analysis |
| 695 ## - | |
| -- | Harmonic distortion |
| 695 ## - | |
| -- | Heuristic algorithms |
| 695 ## - | |
| -- | Impedance |
| 695 ## - | |
| -- | Integrated circuit interconnections |
| 695 ## - | |
| -- | Integrated circuit modeling |
| 695 ## - | |
| -- | Integrated circuits |
| 695 ## - | |
| -- | Interpolation |
| 695 ## - | |
| -- | Inverters |
| 695 ## - | |
| -- | Layout |
| 695 ## - | |
| -- | Libraries |
| 695 ## - | |
| -- | Load modeling |
| 695 ## - | |
| -- | Logic gates |
| 695 ## - | |
| -- | MOS devices |
| 695 ## - | |
| -- | Macrocell networks |
| 695 ## - | |
| -- | Manufacturing |
| 695 ## - | |
| -- | Mathematical model |
| 695 ## - | |
| -- | Matrices |
| 695 ## - | |
| -- | Matrix decomposition |
| 695 ## - | |
| -- | Merging |
| 695 ## - | |
| -- | Microcomputers |
| 695 ## - | |
| -- | Microwave filters |
| 695 ## - | |
| -- | Mirrors |
| 695 ## - | |
| -- | Monte Carlo methods |
| 695 ## - | |
| -- | Niobium |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Gielen, Georges. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Rutenbar, Rob A., |
| Dates associated with a name | 1957- |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Antao, Brian. |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | John Wiley & Sons, |
| Relator term | publisher. |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | IEEE Xplore (Online service), |
| Relator term | distributor. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Print version: |
| International Standard Book Number | 9780471227823 |
| 856 42 - ELECTRONIC LOCATION AND ACCESS | |
| Materials specified | Abstract with links to resource |
| Uniform Resource Identifier | <a href="https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5265766">https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5265766</a> |
No items available.