Monolithic phase-locked loops and clock recovery circuits : (Record no. 40092)
[ view plain ]
| 000 -LEADER | |
|---|---|
| fixed length control field | 11058nam a2201945 i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 5263221 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | IEEE |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20230927112345.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS | |
| fixed length control field | m o d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr |n||||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 100317t20151996nyua ob 001 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9780470545331 |
| Qualifying information | electronic |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 9780780311497 |
| Qualifying information | |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 047054533X |
| Qualifying information | electronic |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1109/9780470545331 |
| Source of number or code | doi |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (CaBNVSL)mat05263221 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (IDAMS)0b000064810c33b9 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | CaBNVSL |
| Language of cataloging | eng |
| Description conventions | rda |
| Transcribing agency | CaBNVSL |
| Modifying agency | CaBNVSL |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3815/364 |
| 245 00 - TITLE STATEMENT | |
| Title | Monolithic phase-locked loops and clock recovery circuits : |
| Remainder of title | theory and design / |
| Statement of responsibility, etc. | edited by Behzag Razavi. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | New York : |
| Name of producer, publisher, distributor, manufacturer | IEEE Press, |
| Date of production, publication, distribution, manufacture, or copyright notice | c1996. |
| 264 #2 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | [Piscataqay, New Jersey] : |
| Name of producer, publisher, distributor, manufacturer | IEEE Xplore, |
| Date of production, publication, distribution, manufacture, or copyright notice | [1996] |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1 PDF (ix, 498 pages) : |
| Other physical details | illustrations. |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | electronic |
| Source | isbdmedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Source | rdacarrier |
| 500 ## - GENERAL NOTE | |
| General note | "A selected reprint volume." |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE | |
| Bibliography, etc. note | Includes bibliographical references and indexes. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Preface -- Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits -- A Tutorial (B. Razavi) -- BASIC THEORY -- Theory of AFC Synchronization (W. Gruen) -- Color-Carrier Reference Phase Synchronization Accuracy in NTSC Color Television (D. Richman) -- Charge-Pump Phase-Locked Loops (F. Gardner) -- z-Domain Model for Discrete-Time PLLs (J. Hein & J. Scott) -- Analyze PLLs with Discrete Time Modeling (J. Kovacs) -- Properties of Frequency Difference Detectors (F. Gardner) -- Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery (D. Messerschmitt) -- Analysis of Phase-Locked Timing Extraction Circuits for Pulse Code Transmission (E. Roza) -- Optimization of Phase-Locked Loop Performance in Data Recovery Systems (R. Co & J. Mulligan) -- Noise Properties of PLL Systems (V. Kroupa) -- PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design (B. Kim, et al.) -- Practical Approach Augurs PLL Noise in RF Synthesizers (M. O'Leary) -- The Effects of Noise in Oscillators (E. Hafner) -- A Simple Model of Feedback Oscillator Noise Spectrum (D. Leeson) -- Noise in Relaxation Oscillators (A. Abidi & R. Meyer) -- Analysis of Timing Jitter in CMOS Ring Oscillators (T. Weigandt, et al.) -- Analysis, Modeling, and Simulation of Phase Noise in Monolithic Voltage-Controlled Oscillators (B. Razavi) -- BUILDING BLOCKS -- Start-up and Frequency Stability in High-Frequency Oscillators (N. Nguyen & R. Meyer) -- MOS Oscillators with Multi-Decade Tuning Range and Gigahertz Maximum Speed (M. Banu) -- A Bipolar 1 GHz Multi-Decade Monolithic Variable-Frequency Oscillator (J. Wu) -- A Digital Phase and Frequency Sensitive Detector (J. Brown) -- A 3-State Phase Detector Can Improve Your Next PLL Design (C. Sharpe) -- GaAs Monolithic Phase/Frequency Discriminator (I. Shahriary, et al.) -- A New Phase-Locked Loop Timing Recovery Method for Digital Regenerators (J. Bellisio) -- A Phase-Locked Loop with Digital Frequency Comparator for Timing Signal Recovery (J. Afonso, et al.). |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Clock Recovery from Random Binary Signals (J. Alexander) -- A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s (A. Pottbacker, et al.) -- A Self-Correcting Clock Recovery Circuit (C. Hogge) -- MODELING AND SIMULATION -- An Integrated PLL Clock Generator for 275 MHz Graphic Displays (G. Gutierrez & D. DeSimone) -- The Macro Modeling of Phase-Locked Loopes for the SPICE Simulator (M. Sitkowski) -- Modeling and Simulation of an Analog Charge Pump Phase-Locked Loop (S. Can & Y. Sahinkaya) -- Mixed-Mode Simulation of Phase-Locked Loops (B. Antao, et al.) -- Behavioral Representation for VCO and Detectors in Phase-Lock Systems (E. Liu & A. Sangiovanni-Vincentelli) -- Behavioral Simulation Techniques for Phase/Delay-Locked Systems (A. Demir, et al.) -- PHASE-LOCKED LOOPS -- A Monolithic Phase-Locked Loop with Detection Processor (E. Murthi) -- A 200-MHz CMOS Phase-Locked Loop with Dual Phase Detectors (K. Ware, et al.) -- High-Frequency Phase-Locked Loops in Monolithic Bipolar Technology (M. Soyuer & R. Meyer) -- A 6-GHz Integrated Phase-Locked Loop Using AlGaAs/GaAs Heterojunction Bipolar Transistors (A. Buchwald, et al.) -- A 6-GHz 60-mW BiCMOS Phase-Locked Loop with 2-V Supply (B. Razavi & J. Sung) -- Design of PLL-Based Clock Generation Circuits (D. Jeong) -- A Variable Delay Line PLL for CPU-Coprocessor Synchronization (M. Johnson & E. Hudson) -- A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors (I. Young, et al.) -- A Wide-Bandwidth Low-Voltage PLL for PowerPC Microprocessors (J. Alvarez, et al.) -- A 30-128 MHz Frequency Synthesizer Standard Cell (R. Bitting & W. Repasky) -- Cell-Based Fully Integrated CMOS Frequency Synthesizers (D. Mijuskovic, et al.) -- Fully-Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and ?50 psec Jitter (I. Novof, et al.) -- PLL Design for a 500 MB/s Interface (M. Horowitz, et al.) -- CLOCK AND DATA RECOVERY CIRCUITS -- An Analog PLL-Based Clock and Data Recovery Circuit with High Input Jitter Tolerance (S. Sun). |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-aL1/4m CMOS (B. Kim, et al.) -- A BiCMOS PLL-Based Data Separator Circuit with High Stability and Accuracy (S. Miyazawa, et al.) -- A Versatile Clock Recovery Architecture and Monlithic Implementation (L. De Vito) -- A 155-MHz Clock Recovery Delay- and Phase-Locked Loop (T. Lee & J. Bulzacchelli) -- A Monolithic 156 Mb/s Clock and Data Recovery PLL Circuit using the Sample- and-Hold Technique (N. Ishihara & Y. Akazawa) -- A Monolithic 480 Mb/s Parallel AGC/Decision/Clock Recovery Circuit in 1.2-aL1/4m CMOS (T. Hu & P. Gray) -- A Monolithic 622 Mb/sec Clock Extraction and Data Retiming Circuit (B. Lai & R. Walker) -- A 660 Mb/s CMOS Clock Recovery Circuit with Instantaneous Locking for NRZ Data and Burst-Mode Transmission (M. Banu & A. Dunlop) -- A Monolithic 2.3-Gb/s 100-mW Clock and Data Recovery Circuit in Silicon Bipolar Technology (M. Soyuer) -- A 50 MHz Phase- and Frequency-Locked Loop (R. Cordell, et al.) -- NMOS ICs for Clock and Data Regeneration in Gigabit-per-Second Optical-Fiber Receivers (S. Enam & A. Abidi) -- A PLL-Based 2.5-Gb/s Clock and Data Regenerator IC (H. Ransijn & P. O'Connor) -- A 2.5-Gb/sec 15-mW BiCMOS Clock Recovery Circuit (B. Razavi & J. Sung) -- An 8 GHz Silicon Bipolar Clock Recovery and Data Regenerator IC (A. Pottbacker & U. Langmann) -- Author Index -- Subject Index -- Editor's Biography. |
| 506 1# - RESTRICTIONS ON ACCESS NOTE | |
| Terms governing access | Restricted to subscribers or individual electronic text purchasers. |
| 530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE | |
| Additional physical form available note | Also available in print. |
| 538 ## - SYSTEM DETAILS NOTE | |
| System details note | Mode of access: World Wide Web |
| 588 ## - SOURCE OF DESCRIPTION NOTE | |
| Source of description note | Description based on PDF viewed 12/21/2015. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Phase-locked loops |
| General subdivision | Design and construction. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Timing circuits |
| General subdivision | Design and construction. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Integrated circuits |
| General subdivision | Design and construction. |
| 655 #0 - INDEX TERM--GENRE/FORM | |
| Genre/form data or focus term | Electronic books. |
| 695 ## - | |
| -- | Accuracy |
| 695 ## - | |
| -- | Active circuits |
| 695 ## - | |
| -- | Active filters |
| 695 ## - | |
| -- | Amplitude modulation |
| 695 ## - | |
| -- | Analytical models |
| 695 ## - | |
| -- | Approximation methods |
| 695 ## - | |
| -- | Band pass filters |
| 695 ## - | |
| -- | Bandwidth |
| 695 ## - | |
| -- | Baseband |
| 695 ## - | |
| -- | BiCMOS integrated circuits |
| 695 ## - | |
| -- | Biographies |
| 695 ## - | |
| -- | Bit rate |
| 695 ## - | |
| -- | Broadband communication |
| 695 ## - | |
| -- | CMOS integrated circuits |
| 695 ## - | |
| -- | Capacitance |
| 695 ## - | |
| -- | Capacitors |
| 695 ## - | |
| -- | Central Processing Unit |
| 695 ## - | |
| -- | Charge pumps |
| 695 ## - | |
| -- | Clocks |
| 695 ## - | |
| -- | Color |
| 695 ## - | |
| -- | Combinational circuits |
| 695 ## - | |
| -- | Computational modeling |
| 695 ## - | |
| -- | Control systems |
| 695 ## - | |
| -- | Crystals |
| 695 ## - | |
| -- | Data mining |
| 695 ## - | |
| -- | Data models |
| 695 ## - | |
| -- | Decoding |
| 695 ## - | |
| -- | Delay |
| 695 ## - | |
| -- | Delay lines |
| 695 ## - | |
| -- | Detectors |
| 695 ## - | |
| -- | Distortion |
| 695 ## - | |
| -- | Driver circuits |
| 695 ## - | |
| -- | Equations |
| 695 ## - | |
| -- | Filtering |
| 695 ## - | |
| -- | Filtering theory |
| 695 ## - | |
| -- | Flip-flops |
| 695 ## - | |
| -- | Frequency control |
| 695 ## - | |
| -- | Frequency locked loops |
| 695 ## - | |
| -- | Frequency measurement |
| 695 ## - | |
| -- | Frequency modulation |
| 695 ## - | |
| -- | Frequency shift keying |
| 695 ## - | |
| -- | Frequency synthesizers |
| 695 ## - | |
| -- | Gain |
| 695 ## - | |
| -- | Gallium arsenide |
| 695 ## - | |
| -- | Generators |
| 695 ## - | |
| -- | HEMTs |
| 695 ## - | |
| -- | Harmonic analysis |
| 695 ## - | |
| -- | Heterojunction bipolar transistors |
| 695 ## - | |
| -- | Hysteresis |
| 695 ## - | |
| -- | ISDN |
| 695 ## - | |
| -- | Indexes |
| 695 ## - | |
| -- | Inductance |
| 695 ## - | |
| -- | Integrated circuit modeling |
| 695 ## - | |
| -- | Inverters |
| 695 ## - | |
| -- | Jitter |
| 695 ## - | |
| -- | Latches |
| 695 ## - | |
| -- | Local oscillators |
| 695 ## - | |
| -- | Logic gates |
| 695 ## - | |
| -- | Low pass filters |
| 695 ## - | |
| -- | MODFETs |
| 695 ## - | |
| -- | MOS devices |
| 695 ## - | |
| -- | Mathematical model |
| 695 ## - | |
| -- | Microwave circuits |
| 695 ## - | |
| -- | Microwave measurements |
| 695 ## - | |
| -- | Microwave oscillators |
| 695 ## - | |
| -- | Mixers |
| 695 ## - | |
| -- | Noise |
| 695 ## - | |
| -- | Noise measurement |
| 695 ## - | |
| -- | Numerical models |
| 695 ## - | |
| -- | Optical signal processing |
| 695 ## - | |
| -- | Oscillators |
| 695 ## - | |
| -- | Particle separators |
| 695 ## - | |
| -- | Passive filters |
| 695 ## - | |
| -- | Phase frequency detector |
| 695 ## - | |
| -- | Phase locked loops |
| 695 ## - | |
| -- | Phase noise |
| 695 ## - | |
| -- | Phase shift keying |
| 695 ## - | |
| -- | Phase shifters |
| 695 ## - | |
| -- | Pixel |
| 695 ## - | |
| -- | Power harmonic filters |
| 695 ## - | |
| -- | Power supplies |
| 695 ## - | |
| -- | Prototypes |
| 695 ## - | |
| -- | Q factor |
| 695 ## - | |
| -- | Quantum wells |
| 695 ## - | |
| -- | RLC circuits |
| 695 ## - | |
| -- | Radiation detectors |
| 695 ## - | |
| -- | Radio frequency |
| 695 ## - | |
| -- | Receivers |
| 695 ## - | |
| -- | Registers |
| 695 ## - | |
| -- | Reliability |
| 695 ## - | |
| -- | Repeaters |
| 695 ## - | |
| -- | Resistors |
| 695 ## - | |
| -- | Ring oscillators |
| 695 ## - | |
| -- | SONET |
| 695 ## - | |
| -- | SPICE |
| 695 ## - | |
| -- | Schottky diodes |
| 695 ## - | |
| -- | Semiconductor device measurement |
| 695 ## - | |
| -- | Semiconductor device modeling |
| 695 ## - | |
| -- | Silicon |
| 695 ## - | |
| -- | Solid modeling |
| 695 ## - | |
| -- | Solid state circuits |
| 695 ## - | |
| -- | Stability criteria |
| 695 ## - | |
| -- | Steady-state |
| 695 ## - | |
| -- | Strontium |
| 695 ## - | |
| -- | Switches |
| 695 ## - | |
| -- | Synchronization |
| 695 ## - | |
| -- | Synthesizers |
| 695 ## - | |
| -- | Temperature measurement |
| 695 ## - | |
| -- | Time frequency analysis |
| 695 ## - | |
| -- | Timing |
| 695 ## - | |
| -- | Timing jitter |
| 695 ## - | |
| -- | Tracking loops |
| 695 ## - | |
| -- | Transfer functions |
| 695 ## - | |
| -- | Transistors |
| 695 ## - | |
| -- | Tuning |
| 695 ## - | |
| -- | Varactors |
| 695 ## - | |
| -- | Voltage control |
| 695 ## - | |
| -- | Voltage-controlled oscillators |
| 695 ## - | |
| -- | Wideband |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Razavi, Behzad. |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | John Wiley & Sons, |
| Relator term | publisher. |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | IEEE Xplore (Online service), |
| Relator term | distributor. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Print version: |
| International Standard Book Number | 9780780311497 |
| 856 42 - ELECTRONIC LOCATION AND ACCESS | |
| Materials specified | Abstract with links to resource |
| Uniform Resource Identifier | <a href="https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5263221">https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5263221</a> |
No items available.