RTL hardware design using VHDL : (Record no. 40049)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 06176nam a2201165 i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 5237648 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | IEEE |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20230927112344.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS | |
| fixed length control field | m o d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr |n||||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 151221s2006 njua ob 001 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9780471786412 |
| Qualifying information | ebook |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9786610448104 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 6610448108 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 9780471720928 |
| Qualifying information | |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 0471720925 |
| Qualifying information | alk. paper |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 0471786411 |
| Qualifying information | electronic |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 047178639X |
| Qualifying information | electronic |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 9780471786399 |
| Qualifying information | electronic |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1002/0471786411 |
| Source of number or code | doi |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (CaBNVSL)mat05237648 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (IDAMS)0b00006481095a71 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | CaBNVSL |
| Language of cataloging | eng |
| Description conventions | rda |
| Transcribing agency | CaBNVSL |
| Modifying agency | CaBNVSL |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.39/2 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Chu, Pong P., |
| Dates associated with a name | 1959- |
| 245 10 - TITLE STATEMENT | |
| Title | RTL hardware design using VHDL : |
| Remainder of title | coding for efficiency, portability, and scalability / |
| Statement of responsibility, etc. | Pong P. Chu. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | Hoboken, New Jersey : |
| Name of producer, publisher, distributor, manufacturer | Wiley-Interscience, |
| Date of production, publication, distribution, manufacture, or copyright notice | c2006. |
| 264 #2 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | [Piscataqay, New Jersey] : |
| Name of producer, publisher, distributor, manufacturer | IEEE Xplore, |
| Date of production, publication, distribution, manufacture, or copyright notice | [2006] |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1 PDF (xxiii, 669 pages) : |
| Other physical details | illustrations. |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | electronic |
| Source | isbdmedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Source | rdacarrier |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE | |
| Bibliography, etc. note | Includes bibliographical references (p. 665-666) and index. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Introduction to digital system design -- Overview of hardware description languages -- Basic language constructs of VHDL -- Concurrent signal assignment statements of VHDL -- Sequential statements of VHDL -- Synthesis of VHDL code -- Combinational circuit design : practice -- Sequential circuit design : principle -- Sequential circuit design : practice -- Finite state machine : principle and practice -- Register transfer methodology : principle -- Register transfer methodology : practice -- Hierarchical design in VHDL -- Parameterized design : principle -- Parameterized design : practice -- Clock and synchronization : principle and practice. |
| 506 1# - RESTRICTIONS ON ACCESS NOTE | |
| Terms governing access | Restricted to subscribers or individual electronic text purchasers. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | The skills and guidance needed to master RTL hardware design This book teaches readers how to systematically design efficient, portable, and scalable Register Transfer Level (RTL) digital circuits using the VHDL hardware description language and synthesis software. Focusing on the module-level design, which is composed of functional units, routing circuit, and storage, the book illustrates the relationship between the VHDL constructs and the underlying hardware components, and shows how to develop codes that faithfully reflect the module-level design and can be synthesized into efficient gate-level implementation. Several unique features distinguish the book: * Coding style that shows a clear relationship between VHDL constructs and hardware components * Conceptual diagrams that illustrate the realization of VHDL codes * Emphasis on the code reuse * Practical examples that demonstrate and reinforce design concepts, procedures, and techniques * Two chapters on realizing sequential algorithms in hardware * Two chapters on scalable and parameterized designs and coding * One chapter covering the synchronization and interface between multiple clock domains Although the focus of the book is RTL synthesis, it also examines the synthesis task from the perspective of the overall development process. Readers learn good design practices and guidelines to ensure that an RTL design can accommodate future simulation, verification, and testing needs, and can be easily incorporated into a larger system or reused. Discussion is independent of technology and can be applied to both ASIC and FPGA devices. With a balanced presentation of fundamentals and practical examples, this is an excellent textbook for upper-level undergraduate or graduate courses in advanced digital logic. Engineers who need to make effective use of today's synthesis software and FPGA devices should also refer to this book. |
| 530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE | |
| Additional physical form available note | Also available in print. |
| 538 ## - SYSTEM DETAILS NOTE | |
| System details note | Mode of access: World Wide Web |
| 550 ## - ISSUING BODY NOTE | |
| Issuing body note | Made available online by EBSCO. |
| 588 ## - SOURCE OF DESCRIPTION NOTE | |
| Source of description note | Description based on PDF viewed 12/21/2015. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Digital electronics |
| General subdivision | Data processing. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | VHDL (Computer hardware description language) |
| 655 #0 - INDEX TERM--GENRE/FORM | |
| Genre/form data or focus term | Electronic books. |
| 695 ## - | |
| -- | Adders |
| 695 ## - | |
| -- | Aggregates |
| 695 ## - | |
| -- | Algorithm design and analysis |
| 695 ## - | |
| -- | Application specific integrated circuits |
| 695 ## - | |
| -- | Arrays |
| 695 ## - | |
| -- | Bibliographies |
| 695 ## - | |
| -- | Books |
| 695 ## - | |
| -- | Clocks |
| 695 ## - | |
| -- | Complexity theory |
| 695 ## - | |
| -- | Computational modeling |
| 695 ## - | |
| -- | Computer architecture |
| 695 ## - | |
| -- | Decoding |
| 695 ## - | |
| -- | Delay |
| 695 ## - | |
| -- | Design methodology |
| 695 ## - | |
| -- | Digital systems |
| 695 ## - | |
| -- | Encoding |
| 695 ## - | |
| -- | Field programmable gate arrays |
| 695 ## - | |
| -- | Finite element methods |
| 695 ## - | |
| -- | Generators |
| 695 ## - | |
| -- | Hardware |
| 695 ## - | |
| -- | Hardware design languages |
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| -- | Heuristic algorithms |
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| -- | IEEE standards |
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| -- | Indexes |
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| -- | Integrated circuit interconnections |
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| -- | Integrated circuit modeling |
| 695 ## - | |
| -- | Latches |
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| -- | Libraries |
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| -- | Logic gates |
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| -- | Memory management |
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| -- | Multiplexing |
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| -- | Organizations |
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| -- | Process control |
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| -- | Pulse generation |
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| -- | Radiation detectors |
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| -- | Random access memory |
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| -- | Receivers |
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| -- | Registers |
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| -- | Routing |
| 695 ## - | |
| -- | Sections |
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| -- | Semantics |
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| -- | Sensitivity |
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| -- | Sequential circuits |
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| -- | Skeleton |
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| -- | Software |
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| -- | Software algorithms |
| 695 ## - | |
| -- | Synchronization |
| 695 ## - | |
| -- | Syntactics |
| 695 ## - | |
| -- | Time factors |
| 695 ## - | |
| -- | Timing |
| 695 ## - | |
| -- | Transistors |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | John Wiley & Sons, |
| Relator term | publisher. |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | IEEE Xplore (Online service), |
| Relator term | distributor. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Print version: |
| International Standard Book Number | 9780471720928 |
| 856 42 - ELECTRONIC LOCATION AND ACCESS | |
| Materials specified | Abstract with links to resource |
| Uniform Resource Identifier | <a href="https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5237648">https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5237648</a> |
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